The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a metal-oxide semiconductor field effect transistor (MOSFET) having a recess channel.
A typical semiconductor device has adopted an individual device, such as a MOSFET device, as a switching device. Accordingly, the size of the MOSFET device has decreased as the semiconductor device becomes highly integrated. As a result, in the MOSFET device having a horizontal channel, which is a typical structure, normal operations have become difficult to perform because of a short channel effect (SCE) and a drain induced barrier lower (DIBL) effect derived from the reduced channel length between a source and a drain.
Thus, a MOSFET device having a recess channel (hereinafter referred to as a recess transistor) has been introduced to overcome the limitation of the MOSFET device having the horizontal channel. The recess transistor includes a structure in which a gate is filled in a trench formed in an active region of a substrate. Such recess transistor can reduce the SCE and the DIBL effect by lengthening the channel length even if the scale of integration increases in the device.
FIG. 1 illustrates a cross-sectional view of a typical recess transistor. A cross-sectional view of a double diffused metal-oxide semiconductor (DMOS) is illustrated herein as an example for convenience of description.
The typical DMOS device includes a doped N+ substrate (drain) 10, an N-epitaxial layer 11 doped at a lower concentration than the substrate 10, a gate electrode 13 comprising a conductive polysilicon layer filled in a trench, a gate oxide layer 12 formed to a uniform thickness on an inner surface of the trench below the gate electrode 13, an N+ doped source region 14 formed on both upper sides of the gate electrode 13, and a planarized P-well 15 formed below the N+ doped source region 14. Also, a source metal layer 16 formed to cover the N+ doped source region 14 and a dielectric layer 17 formed below the source metal layer 16 to cover the gate electrode 13 are further included. Reference denotation ‘T1’ refers to a thickness ‘T1’ of a portion of the gate oxide layer 12 formed at a bottom portion of the trench.
However, a gate capacitance may increase in the typical DMOS device because the gate oxide layer 12 is form to a small uniform thickness on inner sidewalls and a bottom surface of the trench. Accordingly, there are limitations in improving a switching speed of the DMOS device functioning as a switching device.